AMD broadens its AI hardware push with next-generation Versal Premium “MoP” SoCs

AMD is positioning a new round of Versal Premium Gen 2 “MoP” system-on-chip devices for AI workloads that need to run in compact, power-efficient environments. The company’s pitch, laid out in a recent report, centers on a memory bump and a platform designed to serve more than one market at a time.

At the center of the update is AMD’s claim that the Versal Premium Gen 2 MoP SoCs can be configured with up to 32GB of LPDDR5X memory, using LPDDR5X as high-bandwidth, low-power mobile-style dynamic memory. AMD is framing the larger memory capacity as a way to support more capable models and data-hungry processing closer to where content or indicates are captured, rather than relying entirely on centralized cloud compute.

MoP, in AMD’s wording, is a “model of platforms” approach meant to let customers tailor system designs around a common silicon base. In practical terms, the devices are intended to support AI inference and related acceleration tasks in systems where engineers may need to balance compute, memory, and platform flexibility.

AMD’s reported targeting spans compact AI systems as well as networking, defense and video workloads. Those categories share requirements that often pressure hardware designers: for networking, systems must keep latency low while sustaining throughput; for defense and video, applications frequently demand deterministic performance and the ability to operate under constrained space and power envelopes.

The report also suggests the company is using this update to broaden its presence in AI-capable embedded and edge hardware, an area where programmable accelerators and heterogeneous architectures are competing with traditional CPU and GPU-centric designs. Versal devices have historically appealed to customers who want custom logic, acceleration, and integrated system building blocks in one platform, particularly when product life cycles and deployment environments vary widely.

What remains unclear from the public-facing description is how much of AMD’s performance story is tied to the memory increase versus other architectural changes. The post does not provide disclosed benchmark figures, power consumption targets, or latency numbers. It also does not name specific customers, reference designs, or evaluation timelines that would indicate when the chips could appear in shipping systems.

There are also no details in the account about pricing, supported software toolchains and compatibility with specific AI frameworks, or the initial set of product configurations beyond the headline memory capacity. For buyers, those items tend to be decisive, especially in defense and video where procurement processes and qualification schedules can be slow and specific to system-level requirements.