Cadence expands collaboration with Intel Foundry on DTCO for Intel 14A, aiming to speed HPC and mobile chip designs

Cadence (NASDAQ: CDNS) said on Monday, June 8, 2026, that it is expanding its collaboration with Intel Foundry to accelerate Design Technology Co-Optimization (DTCO) for Intel 14A process optimization. DTCO is the practice of tuning electronic design automation (EDA) flows alongside the underlying semiconductor process parameters, with the goal of improving performance, power efficiency, and design reliability while reducing rework during tapeout and validation.

The announcement, posted by Yahoo Finance as a market-news item, focuses on advancing DTCO targeting Intel’s next-generation 14A process for both high-performance computing and mobile designs. Cadence did not provide additional granular technical details in the reprinted market item beyond the DTCO framing and the target application areas.

Intel’s own materials describe Intel 14A as building on Intel 18A and introducing RibbonFET 2 transistor structures and PowerDirect backside power delivery technology. Intel also highlights additional Intel 14A enhancements for power efficiency in the Intel 14A-E variant, which is positioned as more targeted than the baseline node. Those process features matter to DTCO because they influence how designers place, route, and time circuits and how power delivery and announcement integrity challenges show up in layout and signoff.

In earlier ecosystem announcements, Intel has emphasized how closely it works with EDA and design partners to support its foundry strategy. A June 2024 Intel Newsroom article described Intel Foundry’s approach as relying on collaboration with partners like Cadence to provide validated EDA tools, design flows, and reusable intellectual property for “silicon-through-package” design, helping customers move from early exploration to production faster.

Intel has also indicated that Intel 14A is already engaging customers in a pre-production stage. In an Intel Newsroom post from April 29, 2025, Intel said it had engaged with lead customers on Intel 14A, distributed an early Intel 14A Process Design Kit (PDK), and that multiple customers expressed intent to build test chips on the new process node. The PDK is the formal interface between a foundry’s process and a chip designer’s tool flows, typically including design rules, device models, and characterization data.

Cadence and Intel have worked together for multiple Intel advanced nodes before. In a 2024 Cadence press release tied to the Intel Foundry Services ecosystem, the companies said they expanded a multiyear strategic agreement to develop customized IP, optimized design flows, and design techniques for Intel 18A featuring RibbonFET gate-all-around transistors and PowerVia backside power delivery, with target markets including AI/ML, high-performance computing, and premium mobile applications.

While the June 8, 2026 market-news post confirms the expanded DTCO collaboration and the Intel 14A target, it does not disclose what specific Cadence products, tool flows, IP blocks, or measurable outcomes (such as improved PPA, tighter timing correlation, or reduced iteration counts) are planned for this particular 14A effort. It also does not provide a timetable for deliverables, nor does it specify whether the work is focused on early PDK readiness, signoff flows, packaging co-design, or other elements of the design-to-manufacturing pipeline.