Intel highlights U.S. advanced packaging push to support next-generation AI chiplets

Intel is positioning its U.S. advanced packaging capacity as a key enabler for next-generation AI semiconductors, arguing that the industry is shifting away from building one monolithic, massive chip toward systems assembled from multiple specialized “chiplets.” In a detailed update from Intel’s newsroom, the company described advanced packaging as the craft of interconnecting those different components so they can operate like a single high-performance unit for workloads that drive modern AI.

Intel’s message centers on what it calls “U.S. Advanced Packaging,” with a focus on its New Mexico facilities, including the Fab 9 advanced packaging site in Rio Rancho. Intel said it has been doing advanced packaging work for years in the United States and abroad, describing it as crucial to producing multi-chip packages used in today’s technology products.

The update also offered a performance scaling goal tied to lithography constraints. At its Rio Rancho, New Mexico advanced packaging facilities, Intel said it is expanding the “reticle limit” scaling of packages to 8x what it described as the industry standard today, and to more than 12x by 2028. Intel did not explain the reticle limit in detail, but the company framed the effort as a way to push physical scaling by making more effective use of multi-chip architectures rather than relying on larger single-die designs.

Intel described the strategic direction as a move toward what it likened to a “silicon mosaic,” where specialized tiles are interconnected in one large package. Katie Prouty, manager of Intel’s Fab 9 advanced packaging facility in New Mexico, said the site has flipped roles over time, noting that Rio Rancho was a leader in 6-inch wafer manufacturing in the 1980s but is now, more than 40 years later, a leader in the United States for advanced packaging. Prouty also said customers are coming to Intel first for advanced packaging, and that delivering for those early customers is intended to build long-term trust in Intel as a foundry.

To illustrate how Intel assembles these multi-chip systems, the company walked through elements of a process it described as Foveros, an advanced packaging approach that connects smaller chip tiles using a silicon interposer, which Intel compared to a “pizza crust.” In Intel’s description of Fab 9 operations, an initial tool is used to attach chiplets onto that interposer, followed by a step likened to baking the assembled system together. After assembly, Intel said overhead robot systems using FOUPs (front-opening unified pods) bring the wafer for a step where epoxy fills under and around the assembled components to help ensure they are pressed together, and then the wafer is diced into individual packages using precision, water-cooled blades.

Intel said one “great part” of the approach is that it allows it to combine chiplets from different designs or technology nodes onto a single wafer, rather than forcing everything into one process. The company tied that flexibility to potential device implications, including using Foveros to enable more power-efficient circuit placement, improve battery life in laptops, support thinner designs, and reduce footprint demands for performance-sensitive edge computing. Intel also said Foveros is relevant beyond client devices, framing it as part of the foundation for AI systems that depend on combining specialized compute building blocks.

Alongside Foveros, Intel described EMIB (Embedded Multi-Die Interconnect Bridge) as another packaging technology used to link specialized chips within a package through tiny silicon bridges. Intel said the approach can connect different chips so they function as a single unit while supplying the power needed for AI and improving manufacturing efficiency and costs. Intel contrasted EMIB with approaches it described as using more expensive silicon interposers for the connection layer, stating that EMIB embeds bridges only where needed, creating its version of the “silicon mosaic” concept.

Intel also highlighted a newer development it called EMIB-T, saying that in 2026 it adds channels through the bridge to deliver power more directly to the chips instead of routing around the bridge. Intel said this improves power efficiency and announcement routing requirements for higher-bandwidth memory (HBM) technologies. In Intel’s framing, “it’s more than speed,” because the company says its foundry approach can mix and match chiplets from different sources directly onto the industry’s largest substrates, enabling large side-by-side AI engines used in data centers.

Intel’s update also pointed to ecosystem and collaboration elements, saying the packaging push includes validated prototypes, ecosystem readiness, and early customer engagement as a path toward domestic leadership in high-volume manufacturing. The company mentioned collaboration combining its advanced packaging expertise with Lens Technology’s precision glass processing capabilities for enhanced performance in future AI and data center workloads.

Still, key details were not fully disclosed in the newsroom write-up. Intel did not provide specific customer names, contract values, unit volumes, or production timelines tied to particular products, and it did not define how its 8x and 12x “reticle limit” scaling targets translate into specific chip form factors or performance metrics. The company also did not quantify yields, manufacturing capacity, or the share of advanced packaging spend captured by the New Mexico sites within its overall foundry roadmap.

Looking ahead, investors and customers will likely watch whether Intel’s packaging scaling targets, Foveros and EMIB-T technical advantages, and early customer engagement translate into measurable production outcomes for real AI and data center workloads. Intel’s emphasis on domestic advanced packaging capacity suggests the company wants to be more than a design provider, aiming to secure its role in the manufacturing bottleneck that advanced chiplet-based architectures create.

What is Intel’s “advanced packaging” focus? Intel described advanced packaging as the interconnection of multiple specialized chips into a single unit for high-performance workloads.

How does Intel describe its “silicon mosaic” approach? Intel said it uses specialized tiles, or chiplets, interconnected into one massive package rather than relying on a single large chip.

What are the technologies referenced? Intel discussed Foveros (chiplet connections on a silicon interposer) and EMIB (embedded silicon bridges), plus EMIB-T with added power channels for HBM-related routing requirements.

What U.S. site is highlighted? Intel named its Fab 9 advanced packaging facility in Rio Rancho, New Mexico, and linked scaling efforts to those operations.

What scaling targets did Intel cite? Intel said it aims to expand “reticle limit” scaling to 8x the industry standard today, and more than 12x by 2028.