Intel’s Ravi Mahajan traces EMIB’s path from a packaging scaling idea to the AI era’s system bottleneck

Intel has long argued that semiconductor progress is shifting from transistor-only scaling to system-level engineering. In an interview published May 28, 2026, Intel Fellow Ravi Mahajan, a director at Intel Foundry, lays out how that shift connects directly to advanced packaging and to EMIB, or Embedded Multi-die Interconnect Bridge, a technology that uses a small, embedded piece of silicon in a package to link multiple chips at fine pitch. The implication, he says, is that AI performance is increasingly limited by how fast and efficiently data can move between compute, memory, and other components inside the system.

Mahajan frames the packaging renaissance around the reality that AI has changed what “performance” means. For decades, the industry leaned on Moore’s Law, improving performance by shrinking transistors. But he says AI’s rapid growth is driving demands for much higher memory bandwidth and energy efficiency, particularly in managing data traffic. In that world, advanced packaging becomes a new lever because it can bring several specialized chips together in a tightly integrated way, delivering system-level gains that would be hard to reach through monolithic scaling alone.

He describes a personal inflection point from the early 2000s, when packaging was viewed mostly as a supporting function. Mahajan says the question Intel began to ask was whether packaging could have its own version of a scaling roadmap, especially around interconnect density, meaning how many indicates can be efficiently routed into and out of a chip. Traditional routing approaches, he says, were not scaling fast enough to meet future system needs, motivating exploration of silicon-based interconnects placed directly into the package to increase density.

EMIB’s concept, as Mahajan tells it, was to embed a small silicon interconnect bridge within the package so chips can be connected at a very fine pitch. He calls the idea simple in principle but difficult in practice, because it required tackling complex engineering challenges across materials, stress management, and manufacturing. Mahajan says Intel reached confidence to move EMIB into a production program by 2013 and introduced it to the public in the following year, positioning it as a foundational technology for high-performance systems.

The packaging focus matters for AI, Mahajan argues, because AI systems are constrained by data movement speed between compute and memory. As models grow larger and more complex, he says the bottleneck increasingly shifts away from raw compute throughput toward bandwidth and power used to move data. Advanced packaging, he says, can address this by enabling high-density, energy-efficient connections between compute, memory, and switches, improving bandwidth while reducing power consumption. In his view, that is essential to scaling AI workloads that demand performance gains.

For Intel Foundry customers, Mahajan says EMIB and advanced packaging change how systems can be designed. Instead of building a single very large chip, customers can combine multiple smaller chips, each optimized for a particular function, into one integrated package. He adds that this approach can help overcome limits tied to semiconductor lithography, including reticle limits, which are constraints on the maximum pattern size that can be exposed during manufacturing. He also says it can reduce cost and accelerate time to market, and can allow mixing and matching process nodes and, in some cases, even vendors, depending on what best meets system requirements.

Mahajan also emphasizes how Intel’s approach is meant to translate research into high-volume manufacturing. He characterizes advanced packaging as execution at scale, requiring infrastructure, process technology, and engineering depth to make designs manufacturable and reliable. He links that to Intel’s internal integration across disciplines, including design, materials science, process engineering, and manufacturing, suggesting the company is optimizing the entire packaged system rather than individual components in isolation.

Several challenges remain as interconnect density rises. Mahajan says higher density increases complexity across materials, assembly, and system integration, and that reliability must be maintained across many components. He also highlights thermal performance at very high power levels, ongoing yield considerations as designs become more intricate, and power delivery, which he calls another major challenge as systems scale, since efficient power delivery becomes as important as efficient data movement.

Mahajan does not provide specific performance numbers, customer deployment timelines, or manufacturing yield targets in the interview. The article also does not disclose details about the exact breadth of EMIB adoption across Intel Foundry offerings or the quantitative trade-offs versus alternative packaging approaches. For readers assessing the pace of impact, the concrete next step is to watch for Intel Foundry disclosures that pair packaging roadmap claims with measurable results, such as validated bandwidth and power improvements in shipping platforms.

Looking forward, Mahajan points to interconnect scaling as a decade-long focus, both electrically and optically, and he mentions work including co-packaged optics, a packaging approach that integrates optical components near computing elements to raise bandwidth and efficiency. He also cites potential from new materials such as glass substrates. In practice, he suggests leadership will come down to integrating complex systems efficiently and reliably at scale, backed by ongoing innovation and broader ecosystem coordination rather than advances made by any single company alone.