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NVIDIA pitches NVLink Fusion as the missing link for semi-custom “XPU” AI factories
The Apex Times

THE APEX TIMES

Business/The Apex Times/Aug 24, 11:31 AM EDT

NVIDIA pitches NVLink Fusion as the missing link for semi-custom “XPU” AI factories

The company says custom AI accelerators face a bottleneck not in chip design, but in scaling the full data-center “factory” that turns new silicon into sustained, cost-efficient production.

AI “factories” are increasingly built around delivered output, not theoretical peak compute. In a new post, NVIDIA argues that teams designing semi-custom accelerators, which it calls XPUs, run into a practical constraint: getting from an XPU concept to a data-center deployment that is fast, reliable, and economical at scale. The company’s answer is NVLink Fusion, a rack-scale approach intended to connect custom XPUs into NVIDIA’s established AI infrastructure so builders can focus on what’s different while relying on proven infrastructure for the rest.

NVIDIA frames the economics of running these factories around tokens per second (how much model output is delivered), tokens per watt (energy efficiency), cost per token (overall unit economics), and utilization and uptime (how consistently the hardware is kept working). According to the post, delivering on those metrics requires an infrastructure design that behaves like a full factory, including scale-up and scale-out networking, rack-scale architecture, production factory software, and a supplier ecosystem. In other words, the performance and cost targets depend on integration across layers, not just the accelerator itself.

At the network and scale-up layer, NVIDIA says performance breaks down when the fabric cannot keep up. For modern workloads that include trillion-parameter models, mixture-of-experts architectures, and agentic AI systems, the post argues that insufficient scale-up networking can lower utilization and raise cost per token. As an example of what it believes “keeping up” looks like, NVIDIA describes sixth-generation NVLink as a high-bandwidth, low-latency networking approach across a 72-XPU domain, claiming that end-to-end XPU-to-XPU transfer latency is 3 times lower than alternatives based on off-the-shelf Ethernet and that packet rate is 10 times higher.

NVIDIA also points to system-level throughput and interactivity via its GB300 NVL72 configuration, saying it delivers significantly higher throughput than configurations that do not use NVL72. The post further describes a forward roadmap for NVLink domains up to 1,152 accelerators and the use of co-packaged optics in future configurations. It adds another integration angle with NVLink-C2C, which is positioned as a way to connect XPUs to NVIDIA Vera CPUs or other ecosystem CPUs, claiming up to 6 times the energy efficiency of a PCIe interface and aiming to reduce barriers between control and compute for agentic systems.

The post repeatedly returns to the same scheduling and operational challenge faced by semi-custom AI projects: turning XPU innovation into data-center deployment is harder than teams often expect. NVIDIA says the effort includes infrastructure validation before construction, coordinating with manufacturing and supply chain realities, and managing serviceability at the rack level. It notes that AI factory planning typically starts with power procurement, facility design, cooling, rack layout, and network architecture, often long before the final accelerator mix is available, warning that committing a data center to one chip can create schedule risk.

NVIDIA says NVLink Fusion is built to let operators move forward with buildout while deferring the precise silicon mix. It describes a unified architecture in which XPU- and GPU-based systems, such as Vera Rubin NVL72, can share rack footprints and core infrastructure elements like networking, cooling, power delivery, and management systems. In the company’s framing, that makes it easier for hyperscalers and AI-native builders to adopt semi-custom designs without forcing every component of the rack to be re-validated and rebuilt as accelerator choices change.

Industry executives quoted in the post emphasize different parts of the same integration story. Tim Wilson of Intel says the program gives customers the ability to choose CPU architecture, performance level, and software capabilities for their workloads. Jack Luoh of QCT and Quanta Computer says that with Vera Rubin NVL72, the companies are looking at “almost 100% automation” in manufacturing line builds, and that “most of those investments” can be leveraged if the XPU leverages NVLink Fusion. MediaTek’s Vince Hu describes decoupling XPU development from the overall rack-level deployment pace. And at the Amazon-affiliated Annapurna Labs, CC Lee says the approach can use proven NVL72 rack design to support time-to-market and provide access to multiple suppliers.

Beyond hardware interconnect, NVIDIA argues that software is required to complete the factory. It mentions NCCL for distributed workloads, and Dynamo and NIXL for disaggregation, along with Mission Control for cluster management, telemetry, and debugging. It also points to its DSX reference architecture for AI factories, which it describes as codesigning buildings, power, cooling, compute, and networking, and to an NVIDIA Omniverse DSX AI Factory Blueprint that provides a digital twin and open reference design for gigawatt-scale AI factories so partners can model facilities and technology before deployment. For serviceability, NVIDIA describes reference compute trays with 100% liquid cooling and no fans, cables, or hoses, and says they can be removed while the rest of the rack remains operational; it similarly describes liquid-cooled NVLink Switch trays designed to keep operation during service.

Even with NVIDIA’s positioning, important details remain unspecified in the post. It does not lay out specific pricing, licensing terms, or customer commitments for NVLink Fusion, nor does it quantify how much time-to-market or cost per token improvements customers see in measured deployments. The performance comparisons it provides are framed around its own architecture and stated benchmarks, leaving open how results translate across different facility configurations, power constraints, workload mixes, and production schedules.

Looking ahead, the key question is whether builders can treat NVLink Fusion as a stable integration layer as semi-custom silicon choices evolve. For data-center operators, the watch items are practical, not theoretical: how quickly rack deployments can be validated when accelerator mix changes, whether service and uptime targets hold in real operating conditions, and how consistently software and networking performance tracks the factory economics NVIDIA associates with tokens-per-watt and cost-per-token. For NVIDIA, the strategy also indicates an attempt to keep its ecosystem at the center of a broader “factory” stack, even as more customers pursue custom XPUs.

Why It Matters

  • If AI builders increasingly pursue semi-custom accelerators, integration and factory-scale networking can become the main schedule risk, not the chip itself.
  • NVLink Fusion could function as a standardized rack-scale bridge that reduces rework when customers iterate on CPU or XPU designs.
  • The approach ties together hardware interconnect, rack management, and distributed software components, which may affect how quickly new model workloads can be deployed at scale.
  • Operators will likely judge the pitch by real-world utilization, power efficiency, and operational reliability, not by peak compute numbers alone.

Sources

Key Facts

  • NVIDIA says AI factory economics are driven by delivered output metrics such as tokens per second and tokens per watt, plus utilization, uptime, and cost per token.
  • The company argues building semi-custom XPU systems is constrained by the effort to design and integrate the entire AI platform, including scale-up/scale-out networking, rack-scale architecture, and production software.
  • NVIDIA cites sixth-generation NVLink as a 72-XPU scale-up networking approach, claiming 3x lower end-to-end latency than Ethernet-based alternatives and 10x higher packet rate.
  • NVIDIA positions NVLink Fusion as a way to connect XPUs into NVIDIA’s NVLink scale-up domain, including NVLink-C2C for connecting to Vera CPUs or other ecosystem CPUs.
  • The post links NVLink Fusion to broader DSX and Omniverse “digital twin” tools for codesigning AI factory facilities, and highlights liquid-cooled rack tray designs for serviceability.

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