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NVIDIA pushes NVLink Fusion deeper into custom AI hardware with NVHBM high-bandwidth memory
The Apex Times

THE APEX TIMES

Business/The Apex Times/Aug 26, 5:31 PM EDT

NVIDIA pushes NVLink Fusion deeper into custom AI hardware with NVHBM high-bandwidth memory

The company says a new NVLink Fusion option, NVHBM, moves the memory controller into the HBM stack to boost bandwidth and reduce power, while making it easier for hyperscalers to qualify semi-custom AI chips.

4 min readEditor-approved Apex article

NVIDIA said it is expanding NVIDIA NVLink Fusion, a platform aimed at helping large customers and AI chip innovators build semi-custom rack-scale systems without starting from scratch on every hardware component. The new emphasis is memory: the company introduced NVHBM, a next-generation high-bandwidth memory technology designed to increase performance and efficiency for AI processing units (XPUs).

In NVIDIA’s view, today’s AI infrastructure bottlenecks are not only about raw compute. As AI workloads grow in complexity, NVIDIA argues that system performance increasingly depends on how compute, memory, storage, networking, and software are designed together. NVLink Fusion is intended to package that integration work behind a common interconnect and system approach, letting partners focus on their own XPU innovation while relying on NVIDIA’s scale-up and scale-out networking, rack-scale systems, and software building blocks.

The company’s new NVHBM approach is built around a change in where the memory controller sits. In traditional HBM architectures, NVIDIA says the memory controller is placed on the XPU die, taking up valuable silicon area that could otherwise be used for additional compute logic. With NVHBM, NVIDIA moves the custom memory controller into the 3D HBM stack itself, rather than keeping it on the XPU.

NVIDIA linked that design shift to tangible performance and efficiency outcomes. The company said NVHBM delivers up to 30% greater memory bandwidth and 15% lower HBM power consumption. It also said the architecture frees up as much as 25% more area on the XPU compute die compared with “standard HBM4E,” a reference point for a commonly discussed HBM generation in the industry.

Beyond the performance claims, NVIDIA presented NVHBM as a standard implementation. The company said it is establishing NVHBM as a widely deployable configuration that is available from multiple memory providers. NVIDIA argued this can reduce the engineering burden required for partners to integrate and qualify custom memory solutions across different suppliers, which it described as a faster route to getting semi-custom AI chips into production.

One of the first applications, according to NVIDIA, will involve Amazon’s Annapurna Labs. NVIDIA said Annapurna Labs will be the first to work on NVHBM as part of a broader collaboration with NVIDIA around NVLink Fusion, including work to enhance performance and efficiency for AI workloads. NVIDIA also quoted Nafea Bshara, vice president of Annapurna Labs, who said the company looks forward to the technology collaboration for future AWS infrastructure designs.

NVIDIA also tied the NVHBM effort to its broader plan for making custom chips work together at the rack level. The company said NVLink Fusion enables partners to connect custom XPUs and CPUs to NVIDIA’s rack-scale platform. In addition to NVIDIA’s own building blocks, it said partners can access NVLink chiplets, NVLink-C2C, NVLink switches, and NVIDIA MGX systems and racks, alongside an ecosystem that includes CPU partners, ASIC designers, system manufacturers, and other technology providers.

The company positioned this expansion as part of a larger pipeline of next-generation AI hardware. NVIDIA said Annapurna Labs will support NVLink Fusion with next-generation Trainium chips starting with Trainium4, allowing Amazon chips and NVIDIA GPUs to work together using a common rack-scale architecture. Separately, NVIDIA said that AWS previously announced support for NVLink Fusion, and that the new memory technology is designed to extend the capability to NVLink Fusion customers.

What NVIDIA did not specify in its announcement is the full product timeline for widespread availability of NVHBM across customer designs, or the specific validation results partners can expect beyond the stated bandwidth, power, and die-area targets. The company also did not provide detailed benchmarking numbers in the post, such as throughput or application-level performance on particular AI models, leaving room for partners to publish their own results as implementations are validated.

For the next phase, investors and customers will likely watch how quickly multiple memory providers can deliver standardized NVHBM components, and whether Annapurna Labs’ first work translates into production-ready AI racks using Trainium4 and NVIDIA GPUs. NVIDIA’s next steps may also hinge on how well the NVHBM approach supports the company’s goal of making semi-custom AI infrastructure a lower-risk, faster-to-deploy path across both hyperscaler deployments and AI-native system builders.

Why It Matters

  • Memory architecture is increasingly a limiting factor for AI systems, so changes like relocating the memory controller may materially affect performance and power at scale.
  • By standardizing NVHBM across suppliers, NVIDIA is trying to reduce the cost and timeline risk of building semi-custom AI chips.
  • If validated designs using NVLink Fusion and Trainium4 proceed as described, it could strengthen the practical interoperability between hyperscaler ASICs and NVIDIA GPUs at the rack level.
  • The move highlights a broader industry shift toward co-designing compute, memory, and interconnects rather than treating them as separate components.

Sources

Key Facts

  • NVIDIA expanded NVLink Fusion with a new memory technology called NVHBM, aimed at boosting memory performance and efficiency for AI processing units.
  • NVHBM integrates NVIDIA’s custom memory controller into the 3D HBM stack instead of placing it on the XPU die.
  • NVIDIA said NVHBM delivers up to 30% greater memory bandwidth and 15% lower HBM power consumption, and can free up to 25% more XPU compute-die area versus standard HBM4E.
  • NVIDIA said it is establishing NVHBM as a standard implementation available from multiple memory providers to reduce integration and qualification effort.
  • Amazon’s Annapurna Labs will be the first partner to work on NVHBM as part of its collaboration with NVIDIA on NVLink Fusion, starting with Trainium4 support for rack-scale, multi-vendor architectures.

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