NVIDIA turns its Vera CPU toward EDA to speed design of next-generation chips

NVIDIA said it is using a purpose-built CPU, called Vera, to accelerate parts of the electronics design automation, or EDA, workflow used to build its next-generation central processing units and graphics processing units. The move targets a bottleneck that often sits outside of the GPU and AI acceleration story, namely the compute-heavy stages where chip designers simulate behavior, formally verify logic and run large regression tests before designs are finalized for fabrication.

In a post published July 27, NVIDIA said it is collaborating with EDA vendors Cadence and Synopsys to optimize critical applications for Vera and to deploy Vera across NVIDIA’s own EDA workflows. NVIDIA frames the effort as a way to shorten the time it takes engineering teams to validate designs, explore alternatives and move toward tapeout, the point when a chip design is completed for manufacturing.

Several EDA categories are described as CPU-dependent even as GPUs and AI speed other design algorithms. NVIDIA singled out logic simulation, formal verification and portions of digital implementation as workloads that can rely on fast individual cores, efficient memory systems and overall throughput. The company also said CPU architecture can influence how quickly teams can work through thousands of iterations typical of semiconductor development.

NVIDIA reported “up to 1.5x” higher performance on selected production-class workflows when Vera was used in two named verification and simulation tools. Cadence Jasper, which NVIDIA described as a formal verification platform that uses “smart proof” technology and machine learning to find and fix bugs earlier in the design cycle, saw up to 1.5x performance on selected workloads. Synopsys VCS, a high-performance functional verification solution used to simulate and validate complex chip designs before fabrication, also saw up to 1.5x performance while using the same number of cores in testing.

Beyond the headline results, NVIDIA said it is working with both Cadence and Synopsys on application profiling, software optimization and system-level tuning. The intent, as described by NVIDIA, is to broaden the gains beyond the specific benchmarks reported, over time, across a wider range of workflows used by chip teams.

Vera itself is described at a system level rather than as a publicly detailed product. NVIDIA said Vera combines 88 custom NVIDIA Olympus CPU cores with a high-efficiency LPDDR5X memory subsystem and a second-generation NVIDIA Scalable Coherent Fabric. In NVIDIA’s description, the configuration is meant to provide strong per-core performance, high memory bandwidth and consistent low latency, which the company says matters for engineering workloads that mix latency-sensitive tasks with large-scale regression testing across compute farms.

NVIDIA also outlined how these EDA steps connect across the design lifecycle. It said that after engineers define a processor’s architecture and microarchitecture, they describe behavior at the register-transfer level, or RTL, then use multiple verification and implementation technologies to transform the design into manufacturable silicon. The stages NVIDIA referenced include logic simulation, formal verification, regression testing and digital implementation, with the company arguing that throughput improvements can help teams identify issues earlier and potentially reduce costly downstream iterations.

The company positioned the deployment of Vera across its own workflows as part of a broader strategy: choosing the compute architecture best suited to each workload. In EDA, NVIDIA said, GPUs and AI continue to accelerate many algorithms, while high-performance CPUs remain essential for the most demanding simulation, verification and implementation tasks. NVIDIA added that it is planning to build on Vera with a next-generation Rosa CPU powered by the NVIDIA Rigel core, while continuing to optimize leading EDA applications across its CPU roadmap.

As with many internal performance announcements, NVIDIA did not provide details such as absolute run times, the exact configuration of the test systems beyond core counts for the comparative tools, the specific chip-design workloads used in the “selected” tests, or whether performance gains translate directly into shorter end-to-end design cycles for all projects. The post also does not specify how those gains would affect broader EDA metrics such as overall schedule, tapeout timelines or development cost.

For now, the practical question for the market is less about a specific chip design and more about the direction of NVIDIA’s compute strategy, especially as it seeks to tighten the loop between silicon design and the software systems that support it. Investors and customers may watch whether NVIDIA continues to formalize these relationships with EDA vendors, expands the set of benchmarks and workflows where it reports results, and indicates how future CPU generations, including Rosa and its Rigel-based core, will carry the performance improvements forward.